The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.
Various multiphase power converters are known having a plurality of phase circuits connected in parallel. Typically, each phase circuit includes a power switch for delivering power to an output load, and a duty cycle controller for controlling the duty cycle of the power switch. These known designs commonly allow input current to be split among the phase circuits, thereby increasing the efficiency of the power converter. In addition, operating the phase circuits at different phase angles can cancel input and output ripple currents of the power converter.
However, the benefits of efficiency and cancellation of the input and output ripple currents can be compromised if the currents in the phase circuits are not balanced. Differences in the resistances of circuit elements such as switches, inductors and printed circuit board trace resistances can cause such unbalanced currents.
Various designs are known that attempt to balance the currents in the phase circuits. For example, some power converters utilize a peak current mode control which attempts to directly control the peak current in each phase circuit.
FIG. 1 illustrates a boost converter 100 implementing the peak current mode control. The boost converter 100 includes a DC input V1 connected to three phase circuits 102a-c, and a synchronous generator 104 which synchronizes each phase circuit 102a-c to operate at a phase angle difference of 120 degrees with respect to the other phase circuits. In addition, the boost converter 100 includes a diode D4, an output load R11, resistors R9 and R10 and a capacitor C4.
The phase circuit 102a includes an inductor L1, switches Q1 and Q2, a power switch Q3, resistors R2-R6 and R8, diodes D1-D3, capacitors C2-C3 and a duty cycle controller IC1. The duty cycle controller IC1 includes an internal voltage error amplifier (not shown), an output pin of the voltage error amplifier COMP, a current sense pin ISNS, an inverting input pin of the voltage error amplifier VFB, an oscillator pin RT/CT, a reference voltage pin VREF and an output pin VOUT which is connected to the power switch Q3 for controlling the duty cycle of the power switch Q3 (i.e., the on-time and the off-time of the power switch Q3). The circuit elements in the phase circuit 102a are identical to the circuit elements in the phase circuits 102b-c, with the exception being that the phase circuits 102b-c do not include the resistor R8 and the capacitor C3.
During operation of the power converter 100, a voltage divider, formed by the resistors R9 and R10, provides a sample of the voltage at the output load R11, which is input into the duty cycle controller IC1 of the phase circuit 102a. The internal voltage error amplifier of the phase circuit 102a calculates and outputs an error voltage signal, which is an amplified difference of the sampled voltage and an internal reference voltage (typically 2.5V). The COMP pin is connected to the output of the internal voltage error amplifier, and thus receives the error voltage signal. The COMP pin of the phase circuit 102a is also connected to the COMP pins of the phase circuits 102b-c. Thus, the error voltage signal for all three phase circuits is substantially the same voltage.
In addition, the current transformer T1 senses a current in the power switch Q3, and a voltage signal proportional to the current in the power switch Q3 is input into the ISNS pin via the diode D1 and the resistor R2. The duty cycle controller IC1 compares the voltage signal at the ISNS pin with a current limiting signal, which is a voltage proportional to the error voltage signal. The power switch Q3 is turned off when the voltage at the ISNS pin is equal to, or exceeds, the current limiting signal.
As recognized by the inventor, however, a disadvantage to the peak current control mode is that the boost converter 100 is inherently unstable when the source impedance is significantly inductive. One known solution is to add a large capacitor, which can be expensive and bulky, across the DC input V1.
Another solution to the instability problem has been to implement a voltage mode control which is illustrated by a boost converter 200 shown in FIG. 2. The boost converter 200 has the DC input V1 connected to three phase circuits 202a-c and the synchronous generator 104 which synchronizes the phase circuits 202a-c to operate at a phase angle difference of 120 degrees with respect to the other phase circuits. In addition, the boost converter 200 includes the diode D4, the output load R11, the resistors R9 and R10 and the capacitor C4.
As shown in FIG. 2, the phase circuit 202a includes the inductor L1, the switches Q1 and Q2, the power switch Q3, the resistors R4, R6-R8 and a resistor R12, the capacitors C2-C3 and the duty cycle controller IC1. The circuit elements in the phase circuit 202a are identical to the circuit elements in the phase circuits 202b-c, with the exception being that the phase circuits 202b-c do not include the resistor R8 and the capacitor C3.
Unlike the peak current mode control, the phase circuits 202a-c do not include a current sensor. Instead, during operation of the boost converter 200, an oscillating waveform signal at the RT/CT pin of the duty cycle controller IC1 is buffered by the switch Q2 and is input into the ISNS pin of the duty cycle controller IC1 via a voltage divider formed by the resistors R7 and R12. The voltage at the ISNS pin is then compared with the current limiting signal. When the voltage of the oscillating waveform signal is equal to, or exceeds the current limiting signal, the power switch Q3 is turned off.
As recognized by the inventor, however, a disadvantage to the voltage mode control is that the currents in the phase circuits 202a-c are poorly balanced, mainly due to slight mismatches between various circuit elements in each phase circuit 202a-c including the duty cycles of each duty cycle controller IC1, the resistances of each of the power switches Q3 and the resistances of each of the inductors L1.
In addition to the peak current mode control and the voltage mode control, other designs are known which attempt to balance phase circuit currents. These designs typically require current comparison circuits such as current error amplifiers, which add to the complexity and/or reduce the efficiency of the power converter.